Architecture of SAP-1 Microprocessor/Computer

Architecture of SAP-1 Microprocessor/Computer

SAP (Simple-As-Possible)-1 is the first stage in the evolution toward modern computers.

 

Architecture

Figure shows the architecture/ structure of SAP-1, a bus organized computer. All register outputs to the W-bus are three states; this allows orderly transfer data. All other register outputs are two-state. These outputs continuously drive the boxes they are connected to.

 

Program Counter

In 8085 microprocessor, program is stored at the beginning of the memory with the first instruction at binary address 0000, then second instruction at address 0001, the third at address 0010, and so on. The program counter, which is part of the control unit, counts from 0000 to 1111. Its job is to send the memory address of the next instruction to be fetched and executed.

 

Operation of PC:

At first run of computer, program counter is reset and the memory address is at 0000. Now, when computer begins to run program counter sends address 0000 to the memory. When the instruction in the address is fetched and executed, memory address is incremented by a bit to get 0001. Again second instruction is fetched and executed from the address 0001 and the memory address is incremented to get 0010. In this way, program counter is acknowledges the track of instruction to be fetched and executed.

Program counter is also something called pointer, as it points to the address from where the instruction are to be fetched and executed with priority.

 

Inputs and MAR (Memory Address Register)

Input and MAR block is located just below the program counter. It includes the address and data switch registers. Switch registers are part of the input unit which allows sending 4 address bits and 8 data bits to the RAM. Instruction and data words are written into RAM before a computer run.

MAR (Memory Address Register) is the part of the SAP-1 memory unit. Address in program counter (PC) is latched into MAR during a computer run. A bit latter, the MAR applies this 4 bits address to the RAM where a read operation is performed.

 

The RAM

The RAM is SAP-1 is a 16×8 static TTL RAM. By 16×8 it means, we can store 16 words of 8 bits each. Programming of RAM is done by means of address and data switch registers. This allows us to store a program and data in the memory before a computer run.

RAM receives 4-bit address from MAR and a read operation is preformed during a computer run. In this way, instruction or data word stored in the RAM is placed on the W bus for use in some other part of the computer.

 

Instruction Register

The instruction register is the part of control unit. Computer starts a memory read operation to fetch an instruction from the memory and instruction register places the addressed memory location on the W bus. In the same time, the instruction register is set up for loading on the next positive clock edge.

The content of instruction register placed on the W bus is split into two nibbles. The upper nibble is a two-state output that goes directly to the block labeled “Controlled-Sequencer”. The lower nibble is a three state output read onto the W bus when needed.

 

Controller-Sequencer

The controller-sequencer unit of SAP-1 microprocessor is the signal controlling and sequencing unit. Controlling in sense that it controls the signals like inputs, outputs, clock pulses, high and low and Sequencing in sense that it organizes the signal in such a sequence that one is triggered after the execution of another. Controller- sequencer is the junction of handling of all signals.

For an instance, when CE’ is low and LA’ is low controller-sequences determines that RAM’s data is loaded to the Accumulator.

 

Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations. The data stored in the accumulator is used for operation in Adder/ Subtracter block and the result is again stored to the accumulator. The accumulator is also identified as register A.

 

Adder/Subtracter

Adder/Subtracter block perform arithmetic operation in Microprocessor. This block takes inputs form Accumulator and/or other registers (B). The result after the operation is stored in Accumulator. Every arithmetic operation performed in this block is with the logic of addition. After performing the operation result is sent to the 8-bit W-bus.

 

B-register

B register is the register used to store 8-bit data for the operation. It is triggered by the clock pulse so as to pass the stored data to the accumulator.

 

Output Register

Output register is connected with binary display unit. This register is loaded with the output of the operation that is passed through W-bus. When a clock pulse is triggered to the register it is send to the binary display unit.

 

Binary Display

Binary display unit is the output device for the SAP-1 microprocessor.