Pin configuration of Intel 8085 Microprocessor

Pin configuration of Intel 8085 Microprocessor

Pin configuration of 8085 Micro-processor

Pin configuration of 8085 Micro-processor

Figure: Pin configuration of 8085 Microprocessor

The Intel 8085 microprocessor is a new generation, complete 8-bit parallel central processing unit (CPU). The 8085 microprocessor uses a multiplexed data bus. The address is split between the 8-bit address bus and 8-bit data bus. Data provided to the microprocessor are in hexadecimal and the instruction code written is known as Assembly Language.

Pin configuration and explanation

  1. Higher order Address Bus A8 – A15: These tri-state lines are outbound only. This explains its functionality of notating only address of the instruction and data. They provide the upper 8-bits of the 16-bit wide address which only identifies one unique 1-byte within the microprocessor’s address space, or the 8-bit address of an input/output device. Sixteen address lines provide an address space of 65,536 locations i.e. numerically 2^16 = 65,536.
  2. Multiplexed Address-Data Lines AD0 – AD7: These tri-state lines can perform as both inbound as well as outbound. These Address-Data lines provide a multiplexing between the lower bits of the 16-bit wide address first in machine cycle and then 8 data bits in the cycle. To transfer of data these lines can be used as either inbound or outbound depending on the nature of the machine cycle, but when containing address it is used only as outbound. Address-data lines are those who contain the 8-bits of an I/O device address during an I/O operation.
  3. Address Latch Enable (ALE): This is a positive going pulse. When the signal is at logic high (1) the multiplexed data and address bus works as an Address bus and when it is at logic low (0), it works as Data bus.
  4. Status Lines S0, S1 and IO/M’ : These signal lines are simply grouped under status lines it is because they serve to indicate the general status of the processor with respect to what function the microprocessor will /or will have to perform depending on the nature of machine cycle. The S0 and S1 lines are made available for circuits which need advanced warning of the ensuring operation, such as very slow RAM or other specialized devices. The IO/M’ line is used to differentiate input output and memory devices. When the line is high (1) it indicates I/O devices and for low (0) it indicates memory devices.
  5. Control Lines – Read (RD’) – Write (WR’): These lines indicate which direction the microprocessor expects to pass data between itself and the external data bus.  Read signal indicate that the selected device is to be read so that the data is available on the data bus and microprocessor is expecting data to be fed to it ; write indicates that the data on the data bus is to be written to the selected device i.e. microprocessor is going to send data away from itself. These lines also serve to time the event, as well as identify its direction.
  6. Ready: This is an input line which may be used as a signal from external RAM that wait state is needed, since the RAM is not able to provide the data or accept it in the time allowed by the microprocessor. The negation of Ready, by being pulled low, will cause the 8085 microprocessor to enter wait state.
  7. Hold and Hold Acknowledgement (HOLD & HLDA): HOLD is a signal that indicates if the interface devices are requesting the DMA signal/control. HLDA is the acknowledgement of HOLD signal given by the microprocessor to the peripheral devices.
  8. Interrupt and Interrupt acknowledgement (INTR & INTA): These lines provide a vectored interrupt capability to the 8085. Upon receipt of INTR, the 8085 will complete the instruction in process, and then generate INTA as it enters the next machine cycle.
  9. RST 5.5, 6.5, 7.5: These three lines are additional interrupt lines which generates an automatic restart, without jamming to vectors in low RAM which are between those used by the normal INTR instruction. They usually transfer the program control to specific memory location.
  10. TRAP: This is a un-mask able interrupt with a fixed vector and has highest priority among all those interrupt signals.
  11. Reset IN and Reset OUT: Reset IN line is generated asynchronously by some sort of external circuit, such as RC network or Reset Switch. Upon receipt of this signal, the 8085 will internally synchronize the Reset with the clock of the processor, and then generate Reset OUT for other devices in the system. When the signal on the Reset IN pin goes low, the microprocessor is reset, and on reset Reset OUT can be used to reset the interface device.
  12. Serial Input Data (SID) and Serial Output Data (SOD): These two lines provide for a single input or output line to/ from the 8085. The SID and SOD lines are simple single bit I/O lines; any timing required to provide external communication via them must be provided by the software.
  13. X1and X2: These two pins provide connection for an external frequency determining circuit to feed the 8085’s clock. This is normally a crystal, although other resonant circuits may be used. X1 alone may be used as a signal input from an external oscillator. The internal oscillator of the 8085 will divide the frequency by two for the system clock.
  14. Clock (CLK): This line provides a system clock signal to external circuits which need to be in synchronization with the microprocessor.
  15. Vcc and Vss:  Vcc represents the power connection for microprocessor with +5V input and Vss represents the ground of the system.

See also:-Architecture of SAP-1 Microprocessor


  1. Really very helpful.. will you post on architecture of intel 8085 microprocessor..

    • Thanks, and yea sure keep visiting we will post it soon

  2. thank u admin really u made us easy to learn…



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